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A/B 6801 SWITCH -- DESIGN REFERENCE
Single-purpose formatter drive with toggle-selectable processor
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For: John Lundy (Lundy Electronics)   |   2026-06-14

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CONCEPT
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Two 6801s share the Gamma board's U24 site. A manual SPDT toggle selects which
one drives the cassette mechanism and holds the other in reset:
   Position A  -> stock 6801 active (normal read/write/load); B held in reset
   Position B  -> formatter 68701 active (blank-tape creation); A held in reset

The Gamma schematic (sheet 1) shows U24 is socketed and marked "6801 OPTIONAL /
68701 OPTIONAL" -- Coleco designed the site to accept either part. This makes a
two-socket mezzanine practical without cutting the main board.

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WHY RESET-HOLD (not power-gating)
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A 6801 held in RESET releases its port outputs and -- critically -- keeps its
AdamNet transmitter silent. Only the active chip participates on AdamNet, so the
shared net can't be corrupted by two transmitters. A reset chip is in a defined,
quiet state; an unpowered chip can back-drive through its protection diodes.
Reset-hold is therefore the safe selection mechanism.

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SIGNAL CLASSIFICATION (from Gamma U24 + cassette schematics)
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SWITCHED OUTPUTS (only the active chip may drive these to J10-J13):
   WRT DATA   tape write data      (timing-critical: 70us bit cell)
   WR0, WR1   write strobes
   TRACK A/B  track select
   SPD SEL    speed select
   GO FWD     motor forward
   GO REV     motor reverse
   BRAKE      motor brake
   STOP0      stop
   AdamNet TX serial transmit (SCI TXD)
   -> ~10 lines. Route through bus switches enabled by the select line.

SHARED INPUTS (safe to fan to BOTH chips; inputs don't contend):
   RD DATA    tape read data
   MSENSE0/1  motor sense
   CIP0/1     cassette-in-place
   STOP1      stop sense
   AdamNet RX serial receive (SCI RXD)
   XTAL       4.0 MHz clock (or give each chip its own crystal)

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BUS SWITCH CHOICE
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Use 74CBT3245 (octal FET bus switch) for the ~10 switched outputs:
   - Near-zero on-resistance and no added logic delay -> preserves the 70us
     WRT DATA bit-cell timing (ordinary buffers would shift thresholds/timing).
   - Two octal packages cover all switched lines with spares.
   - Enable lines driven by the select toggle: one package enabled in A, the
     other in B (or one /OE per chip's output bundle).

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SELECT + RESET STEERING
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   Manual SPDT toggle -> SELECT line (A=low, B=high, or vice-versa).
   SELECT drives:
     - Bus-switch enables: active chip's outputs connected, other's isolated.
     - Reset steering: active chip's /RESET follows the board reset; inactive
       chip's /RESET forced asserted (held low) regardless of board reset.
   Implement reset steering with a small dual gate (e.g. one 74HC00/74HC32
   section per chip) combining board /RESET with the (inverted) select line.
   Add a power-on delay so both chips start reset-asserted until select settles.

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MEZZANINE BILL OF MATERIALS (indicative)
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   2x 40-pin sockets (chip A stock 6801, chip B formatter 68701)
   2x 74CBT3245 octal bus switch (switched outputs)
   1x 74HC00 or 74HC32 (reset steering / select logic)
   1x SPDT toggle (panel mount)
   decoupling caps; optional 2nd 4.0 MHz crystal if not sharing XTAL
   headers to mate with the U24 socket pads on the Gamma board

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OPERATING NOTES
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   - Flip the toggle only with the drive idle (no tape operation in progress).
   - In position B the drive ONLY formats; it will not read/load tapes.
   - Return to A for normal use.
   - Recommend a panel LED per position so the active mode is obvious.

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OPEN ITEMS FOR LUNDY
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   - Resolve U24 socket pinout to mezzanine pad placement from the Gamma PWB
     drawing (41580 assembly / PWB drawing).
   - Confirm whether AdamNet TX/RX are on SCI pins routed through the socket or
     elsewhere on Gamma, to place the AdamNet isolation correctly.
   - Decide shared-XTAL vs per-chip crystal.
   - Bench-confirm the 70us bit cell on WRT DATA through the CBT switch.
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